The present invention generally relates to semiconductor device manufacturing, and more particularly to the fabrication of III-V fins and IV fins having a similar fin pitch and on a shared surface.
The downscaling of the physical dimensions of metal oxide semiconductor field effect transistors (MOSFETs) has led to performance improvements of integrated circuits and an increase in the number of transistors per chip. Multiple gate MOSFET structures, such as fin field effect transistor's (finFETs) and tri-gate structures, have been proposed as promising candidates for 14 nm technology nodes and beyond. In addition, high-mobility channel materials, such as III-V and germanium, have been proposed as technology boosters to further improve MOSFET scaling improvements.
Integration of lattice mismatched semiconductor materials is one path to high performance semiconductor devices such as complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FET) due to their high carrier mobility. For example, the heterointegration of lattice mismatched semiconductor materials with silicon will be useful for a wide variety of device applications. However, disadvantages associated with structural characteristics of lattice mismatched devices can decrease device performance, require additional processes or design constraints to counter-effect such structural characteristics or reduce manufacturing yield.